As pixel sizes are reduced to less than 1.7 μm to meet demand, there are tradeoffs. The primary disadvantages are reduced sensitivity because the pixel area is smaller, and the smaller opening between pixel wires blocks too much light.
For example, referring to FIG. 1, the pixel schematic from U.S. Patent Publication 2008/0062290 A1 is shown. The unit cell has four transfer gates 107, 108, 109, and 110 that control the flow of charge between the floating diffusion and photodiodes 112, 113, 114, and 111, respectively. Transistor 106 resets the floating diffusion to the level of the power supply VDD. Transistor 105 buffers the floating diffusion voltage and the row select transistor 103 switches that voltage onto the output signal line. In this pixel schematic, there are a total of 6 horizontal wires and two vertical wires. If a 1.4 μm pixel size is desired, then the unit cell of 2.8 μm must contain 6 horizontal wires. If the typical metal 2 wire line and space requirement is 0.18 μm, then those 6 wires will occupy 1.80 μm out of 2.8 μm leaving only a 1.0 μm hole for two photodiodes in the pixel unit cell. A 0.5 μm opening for each photodiode is smaller than the wavelength of red light (650 nm). As a result, the pixel quantum efficiency will be very poor.
The opening in the metal wires could be made larger by using 3 or more layers of metal. Camera lenses for cell phones typically have light rays that may be incident at an angle of 25 degrees from normal. A tall stack of metal wires 3 or more layers high will block light incident at 25 degrees from reaching the photodiodes.
The present invention will address the problem of narrow openings between metal wires above photodiodes while at the same time permitting improved sensitivity by summing pixels in low resolution imaging modes.